Simulcast standard multichip memory addressing system

ABSTRACT

The memory addressing system of the present invention incorporates industry standard features for compatibility and adds the capability of using high-density module memory boards exclusively or in combination with current or next generation standard memory modules without increasing system power requirements. The system provides a plurality of standardized memory module circuit board sockets that are electrically connected so as to provide address decoded RAS signals in addition to the standard row and column addressing signals.

BACKGROUND OF THE INVENTION

This invention relates to electronic data processing systems, and inparticular to memory addressing subsystems having a need for relativelylarge amounts of addressable random access memory (RAM). This inventionhas particular utility in providing enhanced, flexible RAM expansioncapacities by providing the equivalent of next generation monolithic RAMdevices packaged in modules of standardized form such asSingle-In-Line-Memory-Modules (SIMMs) at a much earlier point in time(typically three years) using current generation RAM devices packaged inhigh density, multichip memory modules such as Stakpak™ which are thenpackaged in the same standardized form modules. This achievement is donewithout significantly increasing power requirements (same number ofactive devices per memory cycle) or requiring system reconfiguration.Furthermore, the interface is designed in such a way that when nextgeneration RAM devices become available, they can be packaged in thesame standardized form modules and plugged into the same sockets as thehigh density multichip modules.

DISCUSSION OF THE RELATED ART

As personal and business use of stand-alone or networked electronic dataprocessing systems has increased, they are accompanied by moresophisticated software or applications programming, many of which areimposing ever increasing demands for additional fast random accessmemory.

Many of the advances in system design related to enhancements in theprimary processor or CPU, as well as the addition of coprocessors,memory controllers, enhanced busses and bus controllers, cache memoriesand the like. Advances in the microprocessors from the Intel 80286 tothe 80386, 80486, for example, have provided increased capabilities toaddress memory, and the demand for speed has created an ever increasingdemand for more high speed RAM space that can be accessed much fasterthan peripheral memory devices such as hard disks.

Memory expansion boards have been utilized to allow the expansion ofhigh speed RAM available to the CPU. Memory expansion boards includecircuitry necessary to interface expanded memory to the processor via asystem bus. Expansion boards typically include industry-standard socketsadapted to receive one or more memory modules. One such standard packageis known as a Single-In-Line-Memory-Module (SIMM). Standard packagememory boards utilize a plurality of individual memory packages, such asone megabyte or four megabyte chips, assembled on to a small printedcircuit board having a terminal edge portion for connection into asocket provided on the memory expansion board.

A significant limitation in prior art memory expansion systems relatesto the number of sockets that are provided for memory modules and thepower supply available on the system to energize the memory devices.Most systems provide sufficient power supply capability to effectivelyenergize a predetermined maximum number of RAM devices. Often times, thecomputer system has the capability to address and utilize more memorythan either the number of sockets or its power supply will support.Thus, a memory system limitation is imposed that is lower than thatimposed by the CPU and system architecture.

A memory capacity upgrade for these systems is, thus, dependent upon theavailability of the next generation RAM memory technology which willusually increase capacity in the same volume by a factor of four withoutsignificantly increasing power.

It is important in the computer industry to maintain componentinterconnect compatibility. This permits users and designers to upgradesystems using standardized interconnect configurations and to designhardware and software knowing that certain industry standard addressschemes, for example, will be used in standard systems. One suchstandard is the use of row then column address multiplexing circuitrybetween the system bus and RAM arrays. In this scheme, typically amemory controller circuit, including an address register and a timingand control circuit to provide a row address strobe (RAS) and columnaddress strobe (CAS) signal interfaces with the system bus to permit theCPU and other system devices to address main memory. System main memoryis typically an array of dynamic random access memories, arranged inindividual device or modular form.

Depending on the size of the system memory, provision is typically madein the memory address register for a larger number of address lines orpins than required by the system to permit expansion. Expansion requiresthe capability of decoding more memory addresses than presently providedin the system. Typically, more address pins are installed than requiredto address current system requirements to permit both expansion and theuse of certain "reserved" pins for design features and future uses.

Another area of standardization is in the provision of standardizedsockets on expansion circuit boards to receive memory modules. It isdesirable to provide standardized sockets to enable users to obtainmodules from more than one source. Until recently, most memory moduleswere configured to include an array of single element DRAM devices, suchas one megabit chips with each DRAM surface mounted to the modulecircuit board. The module circuit board was provided with an edge-mountinterconnect portion which was plugged into a socket on the expansionboard. The number of pins or interconnects provided to the modulecircuit board and socket was standardized to accommodate typicalmultiplexed addressing and power requirements.

Recently, memory fabrication technology has advanced to provide multipleelement memory devices in vertical "stacks" to form, for example, amodule comprising four or more one megabit DRAMs sharing the same socketor surface mount on the module circuit board. This new technology is thesubject of copending U.S. patent application Ser. No. 07/561,417,commonly owned by the assignee hereof, the contents of which areincorporated herein by reference.

These new multiple-element memory devices permit quadrupling the amountof memory available in the memory modules without increasing the numberof sockets or space requirements for a given module circuit board. Manypresent day systems are unable to take full advantage of this increasedmemory capacity due to system power supply limitations.

The simulcast memory addressing system of the present invention providesa novel way of overcoming and avoiding the power supply limitation andprovides a new standard memory interconnect and addressing configurationthat permits the designer or user to freely substitute and intermix nextgeneration standard module memory circuit boards with the newhigh-density module memory boards.

SUMMARY OF THE INVENTION

The memory addressing system of the present invention incorporatesindustry standard features for compatibility and adds the capability ofusing high-density module memory boards exclusively or in combinationwith current or next generation standard memory modules withoutincreasing system power requirements. The system provides a plurality ofstandardized memory module circuit board sockets that are electricallyconnected so as to provide address decoded RAS signals in addition tothe standard row and column addressing signals. This "simulcast"addressing scheme allows the 4× capacity, next generation memory modulessuch as SIMMs and 4× capacity high-density memory modules, such asStakpaks™ to be plugged into the same socket and operate with the samenumber of active devices in a given memory cycle. This dualconfiguration capability permits the interchange or simultaneous use ofnext generation or high-density modules such as Stakpaks™ mounted inmemory module circuit boards, like SIMMs.

In addition to the high-density memory module sockets, the system of thepresent invention also includes a new decoding circuit which works inconjunction with the industry standard memory interface circuitry suchas an address register and timing and control circuitry. This additionaldecoder provides the ability to decode or select which one of four ormore "levels" on the high-density stacked memory module is to beaddressed during any given address cycle thereby limiting the powerrequirements for high-density modules to the same level required bysingle density standard modules.

In a typical four-high stack system, the decoder is a standard 2:4circuit which uses any two available address lines from the memoryaddress register and the industry standard row address strobe (RAS) toselectively energize one of four levels in the stack. For convenienceand in keeping with industry custom, usually the two address linescorresponding to the two most significant or two least significantaddress bits are used to provide the necessary decoding. These two bitsare then reserved for programming use only when the computer system isequipped with either the high-density memory devices or the nextgeneration memory devices or SIMMs.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic drawing illustrating the system of the presentinvention configured to utilize the two least significant memory addressbits to decode the high-density stack level address.

FIG. 2 is a schematic drawing illustrating the system of the presentinvention configured to utilize the two most significant memory addressbits to decode the high-density stack level address.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to FIG. 1, the letter A designates generally an addressingsystem according to the present invention. System A includes memoryinterface circuitry M which typically is provided in personal computeror work station microprocessor based computer systems. Memory interfacecircuitry M is typically included on a printed circuit board closelyassociated with the system bus 10 and CPU (not shown).

Memory interface M includes an industry-standard timing and controlcircuit 12, memory address register and refresh counter 14, addressmultiplexer 16 and inverter-buffers 18. Timing and control circuit 12may be in the form of an integrated circuit memory controller chip. Theprimary purpose of circuit 12 is to provide industry-standard rowaddress strobe (RAS) and column address strobe (CAS) signals at outputs20 and 22, respectively, which permit standard row and columnmultiplexed addressing. The CAS and BAS signals are provided as inputsto inverter buffers 18 to provide isolated, inverted CAS and RAS outputs24 and 26, respectively. Refresh circuitry can be implemented in avariety of ways. In this example, it is controlled by the timing andcontrol circuitry of circuit 12 with addresses generated by the refreshcounter of circuit 14. The refresh signal from 12 forces all RAS linesof circuit 34 to be concurrently active.

For the sake of illustration, and not limitation, memory addressregister 14 is shown in a twenty-two bit configuration, wherein the twoleast significant output bit lines 28 and 30 are reserved and not usedfor conventional addressing but are instead used to decode and selectone of four memory stack levels to address high-density memory modulesor SIMMs. Memory address register 14 is a conventional register circuitwhich receives address signals via bus 10, stores them, and providesoutput address signals at multiple address lines 32. During refreshcycles, address signals from the refresh counters are provided atmultiple address lines 32.

Inverter-buffers 18 are conventional circuits which are utilized toprovide isolation and industry-preferred negative true (RAS, CAS) rowaddress strobe and column address strobe signals. Memory interface Malso includes a conventional address multiplex circuit 16 which provides2:1 row and column multiplexed output signals on lines A₀ through A₁₀for the twenty-two input address lines.

System A also includes decoder 34, which in the illustrated exemplarysystem, provides a 2:4 decoding from input lines 28 and 30 to enable oneof four RAS output lines RAS₀, RAS₁, RAS₂ or RAS₃. In industry standardrow and column memory multiplexing the RAS signal is provided to thememory device before the CAS signal. In this scheme, it is the RASsignal that energizes the memory device and thus it is the RAS signalwhich creates power demand. The CAS signal merely completes the addressfor the selected location and does not effect power requirements.

System A further includes a plurality of pairs of side-by-sideconfigured SIMM sockets 36 and 38 located conveniently on an expansionboard for example, and electrically connected to the previouslydescribed elements of system A via address lines A₀ through A₁₀, RASlines RAS₀ through RAS₃, and basic RAS, CAS lines 26 and 24,respectively. In the figures an "x" indicates no connection with theSIMM circuitry to the respective line, while a dot indicates aconnection. However, all signals are available at each SIMM socket andany SIMM can be plugged into any socket.

For simplicity, only one pair of sockets 36, 38 is illustrated in thefigures, but it should be understood that typically a plurality of pairsare provided. Socket 38 is shown with a conventional, monolithic memoryelement SIMM. Socket 36 is shown with a high-density, four-high stackedmemory element, for example, as are currently available from theassignee hereof. Minor changes, such as the addition of four moreRAS_(N) lines from decoding one-of-eight row signals to selectone-of-eight memory elements would be necessary to use an eight-highhigh-density memory element SIMM, together with designation of one moreaddress line from register 14 in addition to lines 28 and 30 for inputto decoder 34.

As can be seen in FIG. 1, the conventional SIMM in socket 38 does notinterconnect with RAS lines RAS₀ through RAS₃, but receives conventionalrow and column addressing signals via connections at pins 40 and 42,respectively. Also, the full field of address lines A₀ through A₁₀ areconnected at pins 44. Typically, at the time of first productintroduction not all of address lines A₀ through A₁₀ are utilized, butconnection is provided to accommodate the next generation. Aconventional SIMM in socket 38 would operate in industry standardfashion and would not utilize RAS₀ through RAS₃ inputs.

A conventional sixty-four megabyte SIMM would include capacity for fourmillion addresses, each one hundred-forty-four bits wide. Such aconventional SIMM would typically use thirty-six memory elements, eachhaving four million addresses, with four bits (16 million bits) for eachaddress (4M×4)×36! yielding 4 million×144 bit storage capacity. Incontrast, the high-density sixty-four megabyte SIMM incorporatesthirty-six stacked elements, wherein each stack includes four,one-million by four bit (4 million bits) memory elements (4×1M×4)×36!yielding 4 million×144 bit addresses.

If alternative high-density modules with four, four million by one bitmemory elements (4×4M×1)×36! yielding 4 million×144 bit addresses areused without level select signals RAS₀ through RAS₃, each of the fourhigh stacked elements in the selected stack would be energized on eachaccess thereby requiring approximately four times as much power as inconventional monolithic SIMMs. Since only one element in each four-highstack is required to be energized during any one memory cycle, thesystem of the present invention uses the RAS₀ through RAS₃ decodedinputs to energize only the one level in the selected stack during amemory cycle containing the specified address memory location. In thisway, inexpensive high-density SIMMs can be utilized instead of nextgeneration monolithic SIMMs without increasing power consumption.

Referring to FIG. 1, a high-density SIMM is installed in socket 36. Oneof four level decoding is provided via RAS connections at pins 46. Theconventional RAS signal on connection pin 48 and the address pin A₀ atpin 50 are not used by the high-density SIMM.

Assuming both a high-density and a monolithic SIMM are in use in a givensystem, the simulcast system of the present invention provides a meansto address either form of SIMM. Conventional SIMM addressing is carriedout using RAS, CAS lines 26 and 24 in combination with address lines A₀through A₁₀. High-density SIMM addressing is carried out using RAS₀through RAS₃ to select one of four levels, conventional CAS address line24 and address lines A₁ through A₁₀. Decode circuit 34 is provided witha RAS input at line 52 to provide correct timing for the decoded one offour RAS level select signals.

Turning now to FIG. 2, an alternative embodiment A' is illustrated,wherein like numbers designate similar elements performing similarfunctions. The only difference in this embodiment is the use of the twomost significant address bits for level select decoding.

The foregoing disclosure and description of the preferred embodiment ofthe invention are illustrative and explanatory thereof, and are notintended to suggest limitation of the invention to the specificembodiment shown. As will be appreciated by those of ordinary skill inthe art, various changes in the size, capacity, specific components orcircuit elements may be made without departing from the spirit of theinvention.

I claim:
 1. A memory addressing subsystem for an electronic dataprocessing system of the type including a system bus to communicate avariety of signals between system elements and system memory, saidmemory addressing subsystem comprising:a) a memory address register andrefresh counter coupled to the system bus for receiving a multiple bitmemory address via the system bus, and providing a multiple-bit addressoutput signal in parallel format; b) a timing and control circuitcoupled to the system bus to receive system memory access timing andcontrol input signals and for providing row address strobe, columnaddress strobe and refresh timing and control output signals; c) anaddress multiplex circuit coupled to said memory address register toreceive said multiple-bit address signal and to provide a multiplexedmultiple-bit address output signal in parallel format comprising a rowaddress followed by column address; d) a memory module level decodecircuit, said level decode circuit being coupled to said memory addressregister for receiving a multiple-bit encoded level select input signal;said level decode circuit also being coupled to said timing and controlcircuit to receive said row address strobe and refresh control signalsas inputs; said level decode circuit providing a multiple-bit memorymodule level select output signal in response to said inputs; e) amemory module socket adapted to receive memory modules comprised ofeither single level memory devices or high-density, multiple-levelmemory devices; f) wherein said single level memory devices are coupledto receive said row and column address strobe signals from said timingand control circuit and to receive said multiplexed multiple-bit addressoutput signal from said address multiplex circuit; and g) wherein saidhigh-density, multiple level memory devices are coupled to receive; saidcolumn address strobe signal from said timing and control circuit; saidmultiple-bit memory module level select output signal; and to receivesaid multiplexed multiple-bit address output signal from said addressmultiplex circuit.
 2. The memory address subsystem of claim 1, whereinsaid multiple-bit memory module level select output signal provided bysaid memory module level decode circuit comprises a decoded output levelselect signal or a multiple output level select signal in the case of arefresh cycle.
 3. The memory address subsystem of claim 2, wherein saidmultiple-bit encoded level select input signal to said memory modulelevel decode circuit comprises the least significant bits of themultiple-bit address output signal from said memory address register. 4.The memory address subsystem of claim 2, wherein said multiple-bitencoded level select input signal to said memory module level decodecircuit comprises the most significant bits of the multiple-bit addressoutput signal from said memory address register.
 5. The method ofaddressing system memory, comprising a plurality of memory devices in amulti-level configuration in a computer system of the type including asystem bus, a data processor, a system memory interface circuit, a meansfor generating memory address signals, and a means for generating memorytiming and control signals, said system memory addressing methodcomprising:a) providing conventional row and column address strobesignals to said system memory; b) providing multiple-bit address signalsto said system memory, said address signals including conventional rowand column address specifying bits and also including memory modulelevel select bits; c) providing a level select signal to said systemmemory in response to decoding of said memory module level select bits;said level select signal being utilized to select one of said pluralityof multi-level commonly coupled memory devices comprising said systemmemory for access; and d) providing multiple-bit refresh address signalsto said system memory, said address signals including conventionalrefresh row address bits and also including said memory module levelselect bits. .Iadd.
 6. A memory addressing subsystem for an electronicdata processing system of the type including a system bus to communicatea variety of signals between system elements and system memory, saidmemory addressing subsystem comprising:a) a memory address register andrefresh counter coupled to the system bus for receiving a multiple-bitmemory address via the system bus, and providing a multiple-bit addressoutput signal expressing a memory address; b) a timing and controlcircuit coupled to the system bus to receive system memory access timingand control input signals and for providing row address strobe, columnaddress strobe and refresh timing and control output signals; c) anaddress multiplex circuit coupled to said memory address register toreceive said multiple-bit address output signal and to provide amultiplexed multiple-bit address output signal expressing said memoryaddress; d) a memory module decode circuit, said decode circuit arrangedto receive an encoded select input signal derived from said memoryaddress; said decode circuit also being coupled to said timing andcontrol circuit to receive said row address strobe said refresh timingand control signals as inputs; said decode circuit providing amultiple-bit memory module select output signal in response to saidinputs; e) a memory module socket adapted to receive a memory module andprovide said memory module with said multiple-bit memory module selectoutput signal and an address signal set derived from said multiplexedmultiple-bit address output signal. .Iaddend..Iadd.
 7. A memory unitselection system for a computer, said system comprising:a defined memoryspace having a set of memory addresses; plural memory units designatedwithin said defined memory space; memory interface circuitry forgenerating a multi-bit memory address signal within the set of memoryaddresses; a row address strobe generator producing a row address strobesignal in substantial correspondence with a computer access of saiddefined memory space; a decode circuit responsive to said row addressstrobe signal to produce one of a set of plural row address unit selectstrobe output signals to select an individual one of said plural memoryunits in correspondence with the information content of a unit selectsignal derived from said multi-bit memory address signal..Iaddend..Iadd.
 8. A method for selecting a memory unit within a definedmemory space associated with a computer system, said method comprisingthe steps of:providing a defined memory space having a set of memoryaddresses; designating plural memory units within said defined memoryspace; generating a multi-bit memory address signal within said set ofmemory addresses; deriving a unit select signal set from said multi-bitmemory address signal; generating a row address strobe signal insubstantial correspondence with a computer system access of said definedmemory space; providing a decode circuit having plural row addressselect strobe signals; conveying said unit select signal set and saidrow address strobe signal to said decode circuit to generate, at a statechange of said row address strobe signal, a selected row address selectstrobe signal corresponding to a selected memory unit as determined bythe information content of said unit select signal set. .Iaddend..Iadd.9. The method of claim 8 wherein said unit select signal set is derivedby the decode circuit from said multi-bit memory address signal bydecoding the combination of a signifying row address datum and asignifying column address datum received from said multi-bit addressmemory signal. .Iaddend..Iadd.10. The method of claims 8 or 9 wherein Nmemory units are designated within said defined memory space and saidunit select signal set has X number of bits where:

    2.sup.X =N. .Iaddend..Iadd.11. The method of claim 10 wherein N equals 4 and X equals
 2. .Iaddend..Iadd.12. The method of claim 10 wherein N equals 2 and X equals
 1. .Iaddend.